1. Field of the Invention
The present invention relates to a wireless communication apparatus generating a decoding clock signal using a frequency synthesizer and more particularly relates to the wireless communication apparatus capable of preventing desensitization caused by harmonic of an operation clock signal.
2. Description of the Related Art
Concerning a receiving part in a wireless communication apparatus, when a strong disturbance wave exists near a receiving frequency, desensitization occurs because of amplification degeneration from saturation of a high frequency part or a like, and therefore a receiving sensitivity deteriorates.
Particularly, concerning a wireless selective calling receiver (such as a pager), for example, the wireless communication apparatus having multiple receiving line signal frequencies, since clock signal harmonic generated in a clock signal generating circuit in the wireless selective calling receiver becomes an disturbance wave and desensitization occurs, there are cases in that receiving sensitivity deteriorates as to a part of line signal frequencies.
FIG. 6 is a block diagram showing a conventional wireless communication apparatus, and FIG. 7 is a view showing a relationship between a line signal frequency and a clock signal harmonic frequency in the conventional wireless communication apparatus.
The conventional wireless communication apparatus, as shown in FIG. 6, is provided with a clock signal generating circuit 301, a control section 302, a receiver/demodulator 303, and a nonvolatile memory 304.
The clock signal generating circuit 301 supplies an operating clock for the control section 302.
The control section 302 controls a receiving operation of the receiver/demodulator 303 and executes processes such as decoding for a digital coded signal as a demodulation result from the receiver/demodulator 303.
The receiver/demodulator 303 demodulates received wireless signal and outputs a demodulated signal consisting of a digital coded signal.
The nonvolatile memory 304 memorizes data such as an ID address in the demodulated signal, a receiving line signal frequency in the receiver/demodulator 303 and a like.
Additionally, for example, a frequency synthesizer is used as the clock signal generating circuit 301. In the conventional wireless communication apparatus having multiple receiving line signal frequencies, like a wireless selective calling receiver, in order to convert a frequency of a received signal or a like, it is conventionally used that plural signals having required various frequencies are produced from stable standard frequency signals using a frequency synthesizer when plural station-frequency-signals and a like are generated (refer to Japanese Patent Application Laid-Open No. Hei5-152903, Japanese Patent Application Laid-Open No. Hei9-008688).
Further, recently, a frequency synthesizer is also used as a clock signal generating circuit for generating a clock signal decoding an encoded-received-demodulated signal.
Next, explanations will be given of operation of the conventional wireless communication apparatus with reference to FIG. 6.
A high frequency signal inputted through an antenna (not shown) and consisting of a wave modulated by a predetermined modulation mode is inputted into the receiver/demodulator 303.
The control section 302 controls the receiver/demodulator 303 so that only the high frequency signal of a required line signal frequency in response to data of received line signal frequency memorized in the nonvolatile memory 304.
The receiver/demodulator 303 demodulates the received high frequency signal and then outputs the demodulated signal as a digital signal of a predetermined encoding form.
The control section 302 decodes this encoded signal using an operation clock signal from the clock signal generating circuit 301. In addition, the control section 302 outputs decoded result data onto a display or a like when an ID address in decoded results data coincides with the ID address memorized in the nonvolatile memory 304.
Concerning the wireless communication apparatus shown in FIG. 6, as shown in FIG. 7, a constant range P of front and back of a line signal frequency f0, for example, a range of f0xc2x1xcex94f0 is the range in which desensitization occurs. When a disturbance wave exists in this range, receiving sensitivity deteriorates.
When a harmonic frequency mxc2x7fLKC of a clock signal is within this range, it effects to a received input and becomes the disturbance wave, receiving sensitivity deteriorates compared with a frequency range outside this range.
In the conventional wireless communication apparatus shown in FIG. 6, the frequency fCLK of a clock signal generated in the clock signal generating circuit 301 is approximately constant. Therefore, there is a problem in that receiving sensitivity deterioration can not avoided since a harmonic mxc2x7fCLK of the clock signal enters the frequency range of f0xc2x1xcex94f0 in which desensitization occurs with a used line signal frequency when a number of receiving lines is large.
In view of the above, it is an object of the present invention to provide a wireless communication apparatus having plural receiving line signal frequencies and preventing desensitization caused by harmonic of an operation clock signal.
According to a first aspect of the present invention, there is provided a wireless communication apparatus including a receiver/demodulator for receiving a line signal of a designated frequency and for demodulating the line signal, a control section for decoding a demodulated line signal with a clock signal, and a clock signal generating circuit for supplying the clock signal for the control section, and wherein the control section controls the clock signal generating circuit in response to the line signal frequency to change a frequency of the clock signal so that harmonic of the clock signal does not exist in a desensitization range corresponding to the line signal frequency.
In the foregoing, a preferable mode is one wherein the clock signal generating circuit includes a standard oscillator generating a signal of a standard frequency, a divider for dividing the clock signal, a phase comparator for detecting a phase error between the divided clock signal and a standard frequency signal and a VCO (Voltage Controlled Oscillator) for changing an oscillating frequency in response to the phase error and wherein the frequency of the clock signal outputted from the VCO is changed by changing the dividing number of the divider in accordance with control by the control section.
Also, a preferable mode is one wherein the control section sequentially changes the dividing number of the divider and controls the clock signal generating circuit to generate the clock signal while determining whether a clock signal harmonic frequency exists in the desensitization range corresponding to the line signal frequency in accordance with the line signal frequency or not, so that the clock signal harmonic frequency does not exist in the desensitization range corresponding to the line signal frequency.
Also, a preferable mode is one wherein the control section determines whether the clock signal harmonic frequency is close to an upside or a downside in the desensitization range, and then controls the clock signal harmonic frequency to exist just outside of the desensitization range.
Also, a preferable mode is one wherein the control section calculates a dividing number of dividing part necessary so that the clock signal harmonic frequency does not exist in the desensitization range corresponding to the line signal frequency in response to the line signal frequency.
Also, a preferable mode is one further including a memory for memorizing the calculated dividing number so as to correspond with the line signal frequency, and wherein the control section controls the clock signal generating circuit to generate the clock signal using the memorized dividing number when identical line signal frequency is received.
Also, a preferable mode is one further including a memory for previously memorizing dividing-rate-data of the divider for each division among plural divisions obtained by dividing a receiving-frequency-range, the dividing-rate-data determined so that a clock signal harmonic frequency does not exist in a desensitization range corresponding to all line signal frequencies in each division, and wherein the control section reads the dividing-rate-data corresponding to a received-line-signal-frequency, controls a dividing-rate of the divider in accordance with the dividing-rate-data and controls the clock generating circuit to generate the clock signal.
According to a second aspect of the present invention, there is provided a wireless communication method including a step of receiving a line signal of a designated frequency, a step of demodulating the line signal, a step of changing a frequency of a clock signal in response to a line signal frequency so that harmonic of the clock signal does not exist in a desensitization range corresponding to the line signal frequency, a step of generating the clock signal, and a step of decoding the demodulated line signal with the clock signal.
According to a third aspect of the present invention, there is provided a media storing a program, the program including a step of receiving a line signal of a designated frequency, a step of demodulating the line signal, a step of changing a frequency of a clock signal in response to a line signal frequency so that harmonic of the clock signal does not exist in a desensitization range corresponding to the line signal frequency, a step of generating the clock signal, and a step of decoding the demodulated line signal with the clock signal.
With this configuration, in the wireless communication apparatus, the control section controls a clock signal generating part to change frequency of the clock signal in accordance with the line signal frequency, therefore, harmonic of a clock signal do not enter the desensitization range corresponding to the line signal frequency.
In this case, the clock signal frequency may be controlled in a frequency synthesizer by changing a dividing number of a dividing part so as to change the frequency of the clock signal outputted from the VCO in accordance with control of the control section. This frequency synthesizer includes the standard oscillator generating a standard frequency signal, the dividing part dividing a clock signal, a phase comparison part for detecting a phase error between the divided signal and the standard frequency signal and the VCO changing an oscillating frequency in response to the phase error.
Also, in this case, the control section may sequentially change the dividing number of the dividing part and may control the clock signal generating circuit to generate the clock signal while determining whether a clock signal harmonic frequency exists in the desensitization range corresponding to the line signal frequency or not in accordance with the line signal frequency, so that the clock signal harmonic frequency does not exist in the desensitization range corresponding to the line signal frequency.
Also, a memory part may be provided to previously memorize dividing-rate-data of the dividing part for each division among plural divisions obtained by dividing a receiving-frequency range, the dividing-rate-data determined so that a clock signal harmonic frequency does not exist in a desensitization range corresponding to all line signal frequencies in each division, and the control section may read the dividing-rate-data corresponding to a received-line-signal-frequency, may control a dividing-rate of the dividing part in accordance with the dividing-rate-data and may control the clock generating part to generate the clock signal.
Accordingly, with this configuration, the clock signal frequency is controlled in the clock generating part so that a harmonic frequency of an operation clock signal in the control section does not become close to the line signal frequency and does not enter a frequency range in which desensitization occurs in the receiver/demodulator, therefore, it is possible to prevent receiving-desensitization by influence of clock signal harmonics.